JOB DUTIES:

Set-up, run, and debug block-level, SOC-level as well as full-chip ATPG runs.

Possesses knowledge and then improve upon our DFT architecture for future products.

Work with cross functional groups to verify DFT implementation pre tape-out. Drive successful bring-up of test patterns and features post tape-out. Finally, add to the in-house expertise of DFT to consult with, educate and train design members from other teams on our DFT requirements as well as on how to prepare future designs based on Cavium DFT architecture. Work with the RTL, DFT, physical design, and timing team to implementing modern DFT solutions for leading edge ICs on the latest technology nodes.

REQUIREMENTS: Master's or foreign equivalent degree in Electrical Engineering, Computer Science, Engineering, or a related field and three (3) years of experience in the job offered or in a related occupation.

Experience must include one (1) year with:

1. Working on test platform, including scan patterns;

2. Operating IC RTL design and using Verilog/SystemVerilog

3. Supporting DFT features and modern JTAG standards and implementation

4. Working with board/bench debug features and capabilities;

5. Programming skills with scripting language such as Perl, TCL/TK, Python and SQL or web page development;

6. Maintaining industry standard DFT and design tools with Synopsys.

7. Creating Scan test, functional test, JTAG and other test methodologies.

8. Delivering high-volume test equipment (ATE) and system level test (SLT) results.