Digital Design Engineer to join premier bay area chip company.

Digital Design Engineer to join a bright team of inventors and engineers to develop safer and faster products.

Responsibilities

• Planning: lead digital designer roles, project managing, design block specification, system level simulation, documentation
• Implementation: RTL design in Verilog, lint, clock domain crossing (CDC) analysis, top level integration, synthesis, timing analysis, timing closure, DFT-related tasks
• Verification: work with verification team on planning and execution, simulation, debugging block and system level simulations, formal verification, preparation of technical reviews and product/block documentation
• Flow and methodology: work in a dynamic and interdisciplinary R&D group that influences and guides Rambus’ technical direction by understanding and contributing to flow and methodology development
• Interact with technical leaders of the company and senior staff in engineering, marketing, and corporate development to help ensure successful development of high value technologies and products

Qualifications

• Experience with memory controller, PCIe digital controller, and/or embedded MCU subsystem designs is required
• Bachelor's or Master's Degree in Electrical or Computer Engineering
• 7+ years of relevant digital/ASIC/IC design experience
• Significant Experience with RTL coding in Verilog and/or VHDL
• Significant Experience with standard ASIC software tools (synthesis, simulation, equivalence checking, static timing analysis)
• Strong knowledge of scripting, Linux/Unix environment, and basic C/C++ programming
• Thorough understanding of ASIC design flow
• Successful past digital leadership roles
• Strong design and system knowledge
• Design for verification experience or understanding (assertion based design strategies, code coverage, functional coverage, test plans etc.) would be an asset
• Self-starter and fast learner with excellent interpersonal skills
• Track record of driving technical solutions across organizational boundaries and multiple technical disciplines

Submit resume to

Type: Fulltime

Location: San Jose, CA

Keon Paulino

408.550.2800 x113

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